The present invention relates to a logic circuit design method for generating a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit, a logic design program used to implement the design method, and a semiconductor integrated circuit configured by applying the design method thereto, and particularly to a technique effectively applied to a logic synthesis tool for a data processing semiconductor integrated circuit such as a microcomputer or a data processor.
In a logic circuit which performs logic operations in synchronization with a clock has a data path prepared by disposing sequential circuits before and after a combinational circuit, and causes sequential circuits to perform input/output operations in a predetermined clock period, thereby performing logic operations while sequentially transferring data to the data path in synchronization with the clock. Accordingly, a logic operation time from when data is outputted from one sequential circuit until when the combinational circuit completes a logic operation on the inputted data and needs to shorter than a required clock period. In other words, the logic operation speed of the logic circuit is determined by a clock period required for the largest number of gate stages through which data is transferred from when the data is outputted from one sequential circuit until when the combinational circuit completes a logic operation on the inputted data. Accordingly, it is preferable that the number of gate stages be smaller in the sequential circuit as well. From such a viewpoint, Japanese Unexamined Patent Publication No. Hei 7 (1995)-249968 (Patent Document 1) and Japanese Unexamined Patent Publication No. Hei 8 (1996)-181574 (Patent Document 2) make it possible to decrease the number of gate stages in a clock synchronous sequential circuit itself.